A wide variety of electronic devices includes components that operate using a reference voltage. For example, mobile phones and other wireless devices often comprise components, such as power amplifiers, that rely on a reference voltage for proper operation. Generally speaking, the reference voltage in a system should be as stable as possible, as fluctuations in the voltage can impact the overall performance of the system. Mobile devices pose a particular challenge in this regard because of the wide range of temperatures in which they operate. The reference voltage in such systems should also be relatively insensitive to variations in the supply voltage from which the reference voltage is derived.
Reference voltage circuits have traditionally used Zener diode, bipolar transistor, or junction field effect transistor (JFETs) designs. For example, U.S. Pat. Nos. 5,838,192 and 5,973,550 describe a reference voltage circuit that uses a pair of JFETs having different channel doping densities. JFETs are formed from a doped semiconductor material (for example, n-type silicon) that defines a channel situated between a source contact and a drain contact. An opposite dopant (for example, p-type doping of n-type silicon) is diffused into a side of the channel and forms a gate region. The interface between the two oppositely doped regions thus forms a p-n junction. As known in the art, a depletion region surrounding the p-n junction can be modulated by reverse-biasing the gate region. Thus, by varying the voltage applied to a gate contact attached to the gate region, the size of the depletion region and therefore the size of a conductive region in the channel can be controlled. Further, because the oppositely doped gate region is diffused into the channel during JFET formation, the p-n junction formed is a homojunction with no band gap difference.
In U.S. Pat. Nos. 5,838,192 and 5,973,550, one of the JFETs in the pair has an extra ion implantation in its channel, increasing the doping in the channel and raising the pinchoff voltage for that JFET. The reference voltage circuits described use the difference in gate-to-source voltages between the pair of JFETs to provide a reference voltage. The described circuits, however, are limited to JFET transistors, wherein one of the JFETs in the pair has an extra ion implantation. Further, the described pairs of JETS are of the same type—either both JFETs are depletion-mode type devices or both JETs are enhancement-mode type devices. Moreover, these reference voltage circuits are based on particular JFET constructions, and are not suited for integration into systems using other types of transistor technologies, such as high-speed devices with high electron mobility transistors (HEMTs). For example, the described reference voltage circuits are not well-suited for implementation on the same chip as an electronic component using HEMT transistors, such as, for example, pseudomorphic HEMTs.